PMC-Sierra, Inc.
PRELIMINARY
PM5381 S/UNI-2488
DATASHEET
PMC-2000489
ISSUE 1
SATURN USER NETWORK INTERFACE FOR 2488 MBIT/S
Register 0861H: T8TE APS1 Interrupt Status
Register 0869H: T8TE APS2 Interrupt Status
Register 0871H: T8TE APS3 Interrupt Status
Register 0879H: T8TE APS4 Interrupt Status
Bit
Type
Function
Default
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
FIFOERRI
Unused
Unused
Unused
Unused
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
R
Bit 3
Bit 2
Bit 1
Bit 0
FIFOERRI:
The FIFO overrun/underrun error interrupt indication bit (FIFOERRI) reports a FIFO
overrun/underrun error event. FIFO overrun/underrun errors occur when FIFO logic detects
FIFO read and write pointers in close proximity to each other. FIFOERRI is set to logic 1 on
a FIFO overrun/underrun error. FIFOERRI is set to logic 0 when the T8TE Interrupt status
register is read. This bit does not cause a hardware interrupt on INTB, unless the FIFOERRE
bit is set high.
Proprietary and Confidentail to PMC-Sierra Inc., and for its Customer’s Internal Use
415
PMC [ PMC-SIERRA, INC ]
