S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
Released
Sꢀ Provides a SATURN POS-PHY Level 3 compliant 32-bit datapath interface (clocked up to
104 MHz) with parity support to read packet data from a 2Kbyte FIFO buffer (256 bytes per
channel).
2.5 The SONET Transmitter
Sꢀ Synthesizes the 155.52 MHz transmit clock from a 77.76 MHz reference.
Sꢀ Provides eight differential PECL bit-serial interfaces at 155.52 Mbit/s.
Sꢀ Inserts register programmable path signal labels (C2).
Sꢀ Generates the transmit payload pointers (H1, H2) and inserts path overhead.
Sꢀ Optionally inserts the 16-byte or 64-byte section trace (J0/Z0) sequence and the 16-byte or
64-byte path trace (J1) sequence from internal register banks.
Sꢀ Optionally inserts externally generated data communication channels (D1-D3, D4-D12) via
a 192 kbit/s (D1-D3) serial stream and a 576 kbit/s (D4-D12) serial stream.
Sꢀ Scrambles the transmitted STS-3c/STM-1 streams and inserts the framing bytes (A1, A2).
Sꢀ Optionally inserts register programmable APS bytes.
Sꢀ Provides support allowing two devices to implement 1+1 and 1:N APS.
Sꢀ Inserts path BIP-8 codes (B3), path remote error indications (REI-P), line BIP-24 codes
(B2), line remote error indications (REI-L), and section BIP-8 codes (B1) to allow
performance monitoring at the far end.
Sꢀ Allows forced insertion of all-zeros data (after scrambling) and the corruption of the
section, line, or path BIP-8 codes for diagnostic purposes.
Sꢀ Inserts ATM cells or POS frames into the transmitted STS-3c/STM-1 payload.
2.6 The Transmit ATM Processor
Sꢀ Provides idle/unassigned cell insertion.
Sꢀ Provides HCS generation/insertion, and ATM cell payload scrambling.
Sꢀ Counts number of transmitted and idle cells.
Sꢀ Provides a UTOPIA Level 3 compatible 32-bit wide datapath interface (clocked up to 104
MHz) with parity support for writing cells into an internal 64 ATM cell FIFO buffer (4 cells
per channel).
2.7 The Transmit POS Processor
Sꢀ Supports any packet based link layer protocol using byte synchronous HDLC framing like
PPP, HDLC and Frame Relay.
Sꢀ Performs self-synchronous POS data scrambling using the x43+1 polynomial.
Sꢀ Encapsulates packets within a POS frame.
Sꢀ Performs flag sequence insertion.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
29
PMC [ PMC-SIERRA, INC ]
