S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
Released
Sꢀ Filters and captures the automatic protection switch channel (APS) bytes in readable
registers and detects APS byte failure.
Sꢀ Captures and de-bounces each synchronization status (S1) nibble in a readable register.
Sꢀ Detects signal degrade (SD) and signal fail (SF) threshold crossing alarms based on
received B2 errors.
Sꢀ Extracts the 16-byte or 64-byte section trace (J0/Z0) sequences and the 16-byte or 64-byte
path trace (J1) sequences into internal register banks.
Sꢀ Detects loss of signal (LOS), out of frame (OOF), loss of frame (LOF), line alarm
indication signal (AIS-L), line remote defect indication (RDI-L), loss of pointer (LOP), path
alarm indication signal (AIS-P), path remote defect indication (RDI-P), path extended
remote defect indicator (extended RDI-P).
Sꢀ Counts received section BIP-8 (B1) errors, received line BIP-24 (B2) errors, line remote
error indicates (REI-L), received path BIP-8 (B3) errors and path remote error indications
(REI-P) for performance monitoring purposes.
2.3 The Receive ATM Processor
Sꢀ Extracts ATM cells from the received STS-3c/STM-1 payload using ATM cell delineation.
Sꢀ Provides ATM cell payload de-scrambling.
Sꢀ Performs header check sequence (HCS) error detection , and idle/unassigned cell filtering.
Sꢀ Detects out of cell Delineation (OCD) and loss of cell delineation (LCD) alarms.
Sꢀ Counts number of received cells, idle cells, errored cells and dropped cells.
Sꢀ Provides a UTOPIA Level 3 compatible 32-bit wide datapath interface (clocked up to 104
MHz) with parity support to read extracted cells from an internal 64 ATM cell FIFO buffer
(4 cells per channel).
2.4 The Receive POS Processor
Sꢀ Supports packet based link layer protocols using byte synchronous HDLC framing like PPP,
HDLC and Frame Relay.
Sꢀ Performs self-synchronous POS data de-scrambling on the received STS-3c/STM-1 payload
using the x43+1 polynomial.
Sꢀ Performs flag sequence detection and terminates the received POS frames.
Sꢀ Performs frame check sequence (FCS) validation for CRC-16.ISO-3309 and CRC-32
polynomials.
Sꢀ Performs control escape de-stuffing of the HDLC stream.
Sꢀ Checks for packet abort sequence.
Sꢀ Checks for minimum and maximum packet lengths. Optionally deletes short packets and
marks those exceeding the maximum length as errored.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
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PMC [ PMC-SIERRA, INC ]
