PM5371TUDX
DATA SHEET
PMC-920525
ISSUE 6
SONET/SDH TRIBUTARY UNIT CROSS CONNECT
Register 06H: Parity Error Interrupt Status
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unused
Unused
Unused
Unused
TPERI
BPERI
LPERI
X
X
X
X
X
X
X
X
R
R
R
R
RPERI
This register is used to identify the source of a parity error interrupt and
acknowledge such an interrupt.
RPERI, LPERI, BPERI, TPERI:
These bits are set high when a parity error on their respective input buses is
detected. If enabled, an interrupt will also occur. These bits are cleared low
immediately following a read of this register causing any active interrupt to be
de-asserted. These bits are latching and will remain high following the
detection of a single parity error until this register is read. These bits retain
their event capture functionality when interrupt generation is disabled and
may be polled to detect parity errors. The RPERI bit monitors the SINR bus,
the LPERI bit monitors the SINL bus, the BPERI bit monitors the DINB bus,
and the TPERI bit monitors the DINT bus.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
37
PMC [ PMC-SIERRA, INC ]
