PM5371TUDX
DATA SHEET
PMC-920525
ISSUE 6
SONET/SDH TRIBUTARY UNIT CROSS CONNECT
Register 02H: Clock Monitor
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unused
Unused
Unused
Unused
DINBA
DINTA
X
X
X
X
X
X
X
X
R
R
R
R
SFPA
SCLKA
This register is used to monitor the integrity of TUDX timing input signals.
SCLKA:
The SCLKA bit indicates that SCLK is active when high. SCLKA is set high
by a low to high transition on SCLK and is set low immediately following a
read of this register. This bit is intended to be polled to detect a system failure
that freezes the SCLK signal.
SFPA:
The SFPA bit indicates that SFP is active when high. SFPA is set high by a
SCLK sampled low to high transition on SFP and is set low immediately
following a read of this register. This bit is intended to be polled to detect a
system failure that freezes the SFP signal.
DINTA:
The DINTA bit indicates that DINT bus is active when high. DINTA is set high
when all bits of the DINT[8:0] bus have changed low to high after sampled by
SCLK and is set low immediately following a read of this register. This bit is
intended to be polled to detect a system failure that freezes any of the
DINT[8:0] bits.
DINBA:
The DINBA bit indicates that DINB bus is active when high. DINBA is set
high when all bits of the DINB[8:0] bus have changed low to high after
sampled by SCLK and is set low immediately following a read of this register.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
32
PMC [ PMC-SIERRA, INC ]
