STANDARD PRODUCT
PM5365 TEMAP
DATASHEET
PMC-1991148
ISSUE 3
HIGH DENSITY VT/TU MAPPER
AND M13 MULTIPLEXER
SREFCLK
SC1FP
Input B7
System Reference Clock (SREFCLK). This system
reference clock is a nominal 19.44MHz +/-50ppm 50%
duty cycle clock. This clock is common to both the add
and drop sides of the SBI bus.
When passing transparent virtual tributaries between
the telecom bus and the SBI bus, SREFCLK must be
the same as LREFCLK.
System C1 Frame Pulse (SC1FP). The System C1
Frame Pulse is used to synchronize devices interfacing
to the SBI bus. This signal is common to both the add
and drop sides of the system SBI bus.
I/O
A6
By default, SC1FP is an input. The TEMAP can
alternatively be configured to generate this frame pulse
- as an output on SC1FP - for use by all other devices
connected to the same SBI bus. Note that all devices
interconnected via an SBI interface must be
synchronized to an SC1FP signal from a single
common source.
As an input, SC1FP is sampled on the rising edge of
SREFCLK. It normally indicates SBI mutiframe
alignment, and thus should be asserted for a single
SREFCLK cycle every 9720 SREFCLK cycles or some
multiple thereof (i.e. every 9720*N SREFCLK cycles,
where N is a positive integer). In synchronous SBI
mode, however, SC1FP is used to indicate T1/E1
signaling multiframe alignment, and thus should be
asserted for a single SREFCLK cycle once every 12
SBI mutiframes (48 T1/E1 frames or 116640 SREFCLK
cycles).
As an output, SC1FP is generated on the rising edge of
SREFCLK. It normally indicates SBI mutiframe
alignment by pulsing high once every 9720 SREFCLK
cycles. In synchronous SBI mode, however, SC1FP is
used to indicate T1/E1 signaling multiframe alignment
by pulsing once every 12 SBI mutiframes (48 T1/E1
frames or 116640 SREFCLK cycles).
Proprietary and Confidential to PMC-Sierra, Inc. and for its Customers’ Internal Use
45
PMC [ PMC-SIERRA, INC ]
