STANDARD PRODUCT
PM5365 TEMAP
DATASHEET
PMC-1991148
ISSUE 3
HIGH DENSITY VT/TU MAPPER
AND M13 MULTIPLEXER
Table 41: SBI ADD BUS Timing (Figure 62)
Symbol
Description
Min
Max
Units
SREFCLK Frequency (See Note 6)
19.44
19.44
MHz
-50 ppm
+50 ppm
SREFCLK Duty Cycle
40
4
60
%
ns
tS
All SBI ADD BUS Inputs Set-Up
SBIADD
Time to SREFCLK (See Note 1)
tH
All SBI ADD BUS Inputs Hold Time
to SREFCLK (See Note 2)
0.75
2
ns
ns
ns
SBIADD
t
t
SREFCLK to SAJUST_REQ Valid
20
20
P
SBIADD
SBIADD
(See Notes 3 and 4)
SREFCLK to SAJUST_REQ Tristate 2
(See Note 5)
Z
Notes on SBI Input Timing:
1. When a set-up time is specified between an input and a clock, the set-up
time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4
Volt point of the clock.
2. When a hold time is specified between an input and a clock, the hold time is
the time in nanoseconds from the 1.4 Volt point of the clock to the 1.4 Volt
point of the input.
3. Output propagation delay time is the time in nanoseconds from the 1.4 Volt
point of the reference signal to the 1.4 Volt point of the output.
4. Maximum and minimum output propagation delays are measured with a 100
pF load on all the outputs.
5. Output tristate delay is the time in nanoseconds from the 1.4 Volt point of the
reference signal to the point where the total current delivered through the
output is less than or equal to the leakage current.
6. Note that in Transparent VT mode this clock must be connected to LREFCLK.
In this case, the more stringent specification of +/- 20ppm applies.
Proprietary and Confidential to PMC-Sierra, Inc. and for its Customers’ Internal Use
218
PMC [ PMC-SIERRA, INC ]
