STANDARD PRODUCT
PM5365 TEMAP
DATASHEET
PMC-1991148
ISSUE 3
HIGH DENSITY VT/TU MAPPER
AND M13 MULTIPLEXER
RGAPCLK
tP
RGAP
RDATO
Dashed line RSCLK represents behaviour
when RSCLKR register bit = 1.
Table 39: Line Side Telecom BUS Input Timing (Figure 62)
Symbol
Description
Min
Max
Units
LREFCLK Frequency
19.44
19.44
MHz
-20 ppm
+20 ppm
LREFCLK Duty Cycle
40
60
%
CLK52M Frequency (51.84 MHz)
51.84
51.84
MHz
-50 ppm
+50 ppm
CLK52M Frequency (44.928 MHz)
CLK52M Duty Cycle
44.928
44.928
MHz
-50 ppm
+50 ppm
40
5
60
%
ns
tS
All Telecom BUS Inputs Set-Up
TEL
Time to LREFCLK (See Note 1)
tH
All Telecom BUS Inputs Hold Time
to LREFCLK (See Note 2)
1
ns
TEL
Notes on Telecom Input Timing:
1. When a set-up time is specified between an input and a clock, the set-up
time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4
Volt point of the clock.
2. When a hold time is specified between an input and a clock, the hold time is
the time in nanoseconds from the 1.4 Volt point of the clock to the 1.4 Volt
point of the input.
Proprietary and Confidential to PMC-Sierra, Inc. and for its Customers’ Internal Use
215
PMC [ PMC-SIERRA, INC ]
