STANDARD PRODUCT
PM5365 TEMAP
DATASHEET
PMC-1991148
ISSUE 3
HIGH DENSITY VT/TU MAPPER
AND M13 MULTIPLEXER
The 19.44MHz LREFCLK input is used to generate a nominal 1.544Mb/s or
2.048Mb/s clock over a 2KHz interval as indicated by the LDC1J1V1 input
divided by four. A nominal T1 rate consists of 772 clocks in 500us. A nominal E1
rate consists of 1024 clocks in 500us. Stuff events, as indicated by the RTDM
block, are compensated within the desynchronizer by generating three separate
clocks to construct the faster or slower rate as shown in Table 5.
A mixture of T1 clock cycles is generated using 12 REFCLK cycles (Fast T1
Cycles) and 13 REFCLK cycles (Slow T1 Cycles) to produce an overall rate of
1.544MHz over the 500us period. A mixture of E1 clock cycles is generated using
9 REFCLK cycles (Fast E1 cycles) and 10 REFCLK cycles (Slow E1 cycles) to
produce an overall rate of 2.048MHz over the 500us period. Table 5 shows the
number of fast and slow cycles required to generate all three T1 and E1 rates.
Table 5
- Desynchronizer Clock Generation Algorithm
Clock
Rate
Fast T1 Slow T1
Overall
Fast E1
Slow
E1
Overall E1
Cycles
Cycles
Cycles T1 Cycles Cycles
Cycles
Slow
Nominal
Fast
303
316
329
468
456
444
771
772
773
510
520
530
513
504
495
1023
1024
1025
Pointer justification events, as indicated by the RTDM block, are compensated
within the desynchronizer by advancing or retarding the phase of the generated
fast, slow and nominal clocks during the 2KHz period. Because pointer
justification have a limited frequency of occurrence the phase adjustments are
leaked out slowly. Twelve phase adjustments will remove or add an entire T1
clock whereas nine phase adjustments will remove or add an entire E1 clock.
The number of phase adjustments needed per pointer justification is on average
89.077 for T1 or 65.829 for E1. These pointer adjustments are spread out over a
1 second period.
9.19 DS3 Mapper Drop Side (D3MD)
The DS3 Mapper DROP Side (D3MD) block demaps a DS3 signal from an
STS-1 (STM-0/AU3) payload. The asynchronous DS3 mapping consists of 9
rows every 125 µs (8 KHz). Each row contains 621 information bits, 5 stuff
control bits, 1 stuff opportunity bit, and 2 overhead communication channel bits.
Fixed stuff bytes are used to fill the remaining bytes. The asynchronous DS3
mapping is shown in Table 6.
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89
PMC [ PMC-SIERRA, INC ]
