PM5363 TUPP+622
TUPP+622
DATASHEET
PMC-1981421
ISSUE 4
SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S
INTERFACES
Register 13CH, 23CH, 33CH: RTOP, TU3 Auxiliary RDI Interrupt or TU #1 in
TUG2 #1 to TUG2 #7 RFI Interrupt
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unused
RFI7I
RFI6I
RFI5I
RFI4I
RFI3I
RFI2I
RFI1I
X
0
0
0
0
0
0
0
R
R
R
R
R
R
R
This register is used to identify and acknowledge remote failure indication
interrupts for the tributaries TU #1 in TUG2 #1 to TUG2 #7. It is also used to
identify and acknowledge TU3 auxiliary remote defect indication interrupts.
RFI1I:
The RFI1I bit identify the source of remote defect indication interrupts. In TU3
mode, the RFI1I bit reports and acknowledges auxiliary RDI interrupt of the
TU3 stream. Out of TU3 mode, the RFI1I bit reports and acknowledges RFI
interrupt of TU #1 in TUG2 #1. Interrupts are generated when the received
RFI state changes. The RFI1I bit is set high when a change of RDI state
event occurs and are cleared immediately following a read of this register,
which also acknowledges and clears the interrupt. RFI1I remains valid when
interrupts are not enabled (RFIE set low) and may be polled to detect change
of remote defect indication events.
RFI2I-RFI7I:
The RFI2I to RFI7I bits identify the source of remote failure indication
interrupts. RFI1I to RFI7I bits report and acknowledge RFI interrupt of TU #1
in TUG2 #2 to TUG2 #7, respectively. Interrupts are generated when the
received RFI state changes. An RFIxI bit is set high when a change of RFI
state on the associated tributary (TU #1 in TUG2 #x) occurs and are cleared
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
237
PMC [ PMC-SIERRA, INC ]
