PM5363 TUPP+622
TUPP+622
DATASHEET
PMC-1981421
ISSUE 4
SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S
INTERFACES
Register 37H, 57H, 77H: VTPP, TU #3 in TUG2 #1 to TUG2 #7, LOP Interrupt
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unused
LOP7I
LOP6I
LOP5I
LOP4I
LOP3I
LOP2I
LOP1I
X
0
0
0
0
0
0
0
R
R
R
R
R
R
R
This register is used to identify and acknowledge loss of pointer interrupts for the
tributaries TU #2 in TUG2 #1 to TUG2 #7.
LOP1I-LOP7I:
The LOP1I to LOP7I bits identify the source of loss of pointer interrupts. In
TU3 mode, these bits are unused and will return a logic 0 when read. When
the corresponding TUG2 tributary group is configured for TU2 (VT6) or VT3
mode, the associated LOPxI bit is unused and will return a logic 0 when read.
When operational, the LOP1I to LOP7I bits report and acknowledge LOP
interrupts of TU #3 in TUG2 #1 to TUG2 #7, respectively. Interrupts are
generated upon loss of pointer and upon re-acquisition. An LOPxI bit is set
high when a loss of pointer event on the associated tributary occurs and are
cleared immediately following a read of this register, which also
acknowledges and clears the interrupt. LOPxI remains valid when interrupts
are not enabled (ALARME set low) and may be polled to detect loss of pointer
events.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
181
PMC [ PMC-SIERRA, INC ]
