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PM5363-BI 参数 Datasheet PDF下载

PM5363-BI图片预览
型号: PM5363-BI
PDF下载: 下载PDF文件 查看货源
内容描述: SONET / SDH支路单元荷载处理器, 622兆比特/ s接口 [SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES]
分类和应用: ATM集成电路SONET集成电路SDH集成电路电信集成电路电信电路异步传输模式
文件页数/大小: 459 页 / 3435 K
品牌: PMC [ PMC-SIERRA, INC ]
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PM5363 TUPP+622  
TUPP+622  
DATASHEET  
PMC-1981421  
ISSUE 4  
SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S  
INTERFACES  
inverted, causing downstream pointer processing elements to enter a loss of  
pointer state. The DLOP bit has no effect when the IPAIS bit is set high.  
ALARME:  
The ALARME bit enables loss of pointer and path AIS interrupts for tributary  
TU #3 in the corresponding TUG2. When ALARME is set high, an interrupt is  
generated upon entry to and exit from the LOP and AIS state of the pointer  
interpreter state diagram. Interrupts due to AIS and LOP status change are  
masked when ALARME is set low.  
LOPV:  
The LOPV bit indicates the loss of pointer status of tributary TU #3 in the  
corresponding TUG2.  
PF:  
The PF bit enables pointer follower mode for tributary TU #3 in the  
corresponding TUG2. In pointer follower mode, the tributary FIFO dead-zone  
is collapsed so that any variation in FIFO depth will result in an outgoing  
pointer justification event. Any TU pointer justification event on the  
corresponding incoming tributary, or an AU pointer justification event affecting  
this tributary will cause an outgoing pointer justification event.  
CONFIG[1:0]:  
The CONFIG[1:0] bits are read-only and reflect the values written into the  
corresponding register of TU #1. The configuration specified by the  
CONFIG[1:0] bits are selected as follows:  
CONFIG[1] CONFIG[0] Configuration  
Active TU (VT)  
0
0
1
1
0
1
0
1
TU2 (VT6)  
VT3  
TU12 (VT2)  
TU11 (VT1.5)  
#1  
#1, #2  
#1, #2, #3  
#1, #2, #3, #4  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
180  
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