PM5363 TUPP+622
TUPP+622
DATASHEET
PMC-1981421
ISSUE 4
SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S
INTERFACES
Register 21H-26H, 41H-46H, 61H-66H: VTPP, TU #1 in TUG2 #2 to TUG2 #7,
Configuration and Status
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
CONFIG[1]
CONFIG[0]
PF
LOPV
ALARME
DLOP
1
1
0
X
0
0
0
0
IIDLE
IPAIS
This set of registers reports the status and configures the operational modes of
TU #1 in TUG2 #2 to TUG2 #7. These registers have no effect in TU3 mode.
IPAIS:
The IPAIS bit enables the insertion of path AIS for tributary TU #1 in the
corresponding TUG2. Tributary path AIS is inserted by forcing all ones into all
tributary bytes. The IPAIS bit has no effect when IIDLE is set high.
IIDLE:
The IIDLE bit enables the insertion of path idle for tributary TU #1 in the
corresponding TUG2 . When IIDLE is set high, tributary payload bytes,
including V5 is replaced by an all-zero code. The V5 byte is set to all-zero to
yield correct BIP-2 and to indicate tributary unequipped. The outgoing pointer
is forced to zero. The IIDLE bit has precedence over the IPAIS bit.
DLOP:
The DLOP bit allows downstream pointer processing elements to be
diagnosed. When DLOP is set high, the new data flag (NDF) field of the
outgoing payload pointer in tributary TU #1 in the corresponding TUG2 is
inverted to cause downstream pointer processing elements to enter a loss of
pointer state. The DLOP bit has no effect when the IPAIS bit is set high.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
172
PMC [ PMC-SIERRA, INC ]
