PM5363 TUPP+622
TUPP+622
DATASHEET
PMC-1981421
ISSUE 4
SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S
INTERFACES
11.2 VTPP #1, VTPP #2 and VTPP #3 Registers
Register 20H, 40H, 60H: VTPP, TU3 or TU #1 in TUG2 #1, Configuration and
Status
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
CONFIG[1]
CONFIG[0]
PF
LOPV
ALARME
DLOP
1
1
0
X
0
0
0
0
IIDLE
IPAIS
In TU3 mode (TU3 bit in VTPP Configuration register set high), this register
reports the status and configures operational modes of the TU3 mapped into a
TUG3 handled by the VTPP. Out of TU3 mode, this register reports the status
and configures the operational modes of TU #1 in TUG2 #1.
IPAIS:
The IPAIS bit enables the insertion of path AIS for tributary TU #1 in TUG2 #1
or TU3 depending on whether the VTPP is in TU3 mode. Tributary path AIS is
inserted by forcing all ones into all tributary bytes. The IPAIS bit has no effect
when IIDLE is set high.
IIDLE:
The IIDLE bit enables the insertion of path idle for tributary TU #1 in TUG2 #1
or TU3 depending on whether the VTPP is in TU3 mode. When IIDLE is set
high, tributary payload bytes, including V5 are replaced by an all-zero code.
The V5 byte is set to all-zero to yield correct BIP-2 and to indicate tributary
unequipped. The outgoing pointer is forced to zero. The IIDLE bit has
precedence over the IPAIS bit.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
169
PMC [ PMC-SIERRA, INC ]
