PM5363 TUPP+622
TUPP+622
DATASHEET
PMC-1981421
ISSUE 4
SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S
INTERFACES
Register 27H, 47H, 67H: VTPP, TU3 or TU #1 in TUG2 #1 to TUG2 #7, LOP
Interrupt
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R
R
R
R
R
R
R
Reserved
LOP7I
LOP6I
LOP5I
LOP4I
LOP3I
LOP2I
LOP1I
0
0
0
0
0
0
0
0
This register is used to identify and acknowledge loss of pointer interrupts for the
tributaries TU #1 in TUG2 #1 to TUG2 #7. It is also used to identify and
acknowledge TU3 loss of pointer interrupts.
LOP1I:
The LOP1I bit identifies the source of loss of pointer interrupts. In TU3 mode,
the LOP1I bit reports and acknowledges LOP interrupt of the TU3 pointer. Out
of TU3 mode, the LOP1I bit reports and acknowledges LOP interrupt of TU #1
in TUG2 #1. Interrupts are generated upon loss of pointer and upon re-
acquisition. LOP1I is set high when the corresponding loss of pointer event
occurs and are cleared immediately following a read of this register, which
also acknowledges and clears the interrupt. LOP1I remains valid when
interrupts are not enabled (ALARME set low) and may be polled to detect loss
of pointer events.
LOP2I-LOP7I:
The LOP2I to LOP7I bits identify the source of loss of pointer interrupts. In
TU3 mode, these bits are unused and will return a logic 0 when read. Out of
TU3 mode, the LOP2I to LOP7I bits report and acknowledge LOP interrupt of
TU #1 in TUG2 #2 to TUG2 #7, respectively. Interrupts are generated upon
loss of pointer and upon re-acquisition. An LOPxI bit is set high when a loss of
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
174
PMC [ PMC-SIERRA, INC ]
