PM5363 TUPP+622
TUPP+622
DATASHEET
PMC-1981421
ISSUE 4
SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S
INTERFACES
cleared immediately following a read of this register, which also
acknowledges and clears the interrupt. The LOM2I bit remains valid when
interrupts are not enabled (LOM2E set low) and may be polled to detect out of
frame events.
LOM3I:
The LOM3I bit indicates a change of status in the H4 byte framer. Interrupts
are generated when the H4 framer in tributary payload processor #3 enters
loss of multiframe state and when it re-acquires multiframe alignment. The
LOM3I bit is set high on entry and exit to the loss of multiframe state and is
cleared immediately following a read of this register, which also
acknowledges and clears the interrupt. The LOM3I bit remains valid when
interrupts are not enabled (LOM3E set low) and may be polled to detect out of
frame events.
IPI:
The incoming parity error interrupt bit (IPI) is set high when a parity error is
detected on the incoming parity signal set. If the IPE bit in the STP incoming
configuration register is set high, the interrupt output (INTB) is activated.
When this register is read, IPI (and the corresponding interrupt) is cleared.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
139
PMC [ PMC-SIERRA, INC ]
