PM5363 TUPP+622
TUPP+622
DATASHEET
PMC-1981421
ISSUE 4
SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S
INTERFACES
Register 09H: STP Parity Error and LOM Interrupt
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R
IPI
Unused
LOM3I
LOM2I
LOM1I
Reserved3
Reserved2
Reserved1
0
X
0
0
0
1
1
1
R
R
R
R/W
R/W
R/W
This register provides interrupt status of the H4 byte framers in the three tributary
payload processor and of the input parity checker in the STP.
Reserved[3:1]:
The Reserved[3:1] bits must be set high for the correct operation of the
TUPP+622.
LOM1I:
The LOM1I bit indicates a change of status in the H4 byte framer. Interrupts
are generated when the H4 framer in tributary payload processor #1 enters
loss of multiframe state and when it re-acquires multiframe alignment. The
LOM1I bit is set high on entry and exit to the loss of multiframe state and is
cleared immediately following a read of this register, which also
acknowledges and clears the interrupt. The LOMI bit remains valid when
interrupts are not enabled (LOM1E set low) and may be polled to detect out of
frame events.
LOM2I:
The LOM2I bit indicates a change of status in the H4 byte framer. Interrupts
are generated when the H4 framer in tributary payload processor #2 enters
loss of multiframe state and when it re-acquires multiframe alignment. The
LOM2I bit is set high on entry and exit to the loss of multiframe state and is
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
138
PMC [ PMC-SIERRA, INC ]
