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PM5362-RI 参数 Datasheet PDF下载

PM5362-RI图片预览
型号: PM5362-RI
PDF下载: 下载PDF文件 查看货源
内容描述: SONET / SDH支路单元荷载处理器/性能监控 [SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR / PERFORMANCE MONITOR]
分类和应用: 监控监视器
文件页数/大小: 354 页 / 1028 K
品牌: PMC [ PMC-SIERRA, INC ]
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PM5362TUPP-PLUS  
DATA SHEET  
PMC-951010  
ISSUE 6  
SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR / PERFORMANCE MONITOR  
provisioned value. Path signal label unstable, path signal label mismatch and  
change of path signal label event are identified.  
8.4.1 Clock Generator  
The clock generator derives various clocks from the 19.44 MHz system clock and  
distributes them to other blocks within the tributary payload processor. The  
overall design is totally synchronous, with processing occurring at a 6.48 MHz  
rate in each tributary path overhead processor.  
8.4.2 Timing Generator  
The timing generator identifies the incoming tributary being processed at any  
given point in time. Based on the configuration of the RTOP (it can process  
various mixes of tributary types), the incoming timing generator extracts the STS-  
1 SPE, VC3, or a single TUG3 from a VC4, and identifies the bytes within these  
envelopes that correspond to various types of overhead and those that carry  
specific tributaries to be processed. The identification of specific tributaries  
allows the error monitor and extract blocks to be time-sliced across the mix of  
tributaries present in the incoming data stream.  
8.4.3 Error Monitor  
The error monitor block is a time-sliced state machine. It relies on the timing  
generator block to identify the tributary being processed. The error monitor block  
contains a set of 12-bit counters that are used to accumulate tributary path BIP-2  
errors, and a set of 11-bit counters to accumulate far end block errors (FEBE).  
The contents of the counters may be transferred to a holding RAM, and the  
counters reset under microprocessor control.  
Tributary path BIP-2 errors are detected by comparing the tributary path BIP-2  
bits in the V5 byte extracted from the current multiframe, to the BIP-2 value  
computed for the previous multiframe. BIP-2 errors may be accumulated on a  
block or nibble basis as controlled by software configurable registers. Far end  
block errors (FEBEs) are detected by extracting the FEBE bit from the tributary  
path overhead byte (V5).  
Tributary path remote defect indication (RDI) and remote failure indication (RFI)  
are detected by extracting bit 8 and bit 4 respectively of the tributary path  
overhead byte (V5). The RDI is recognized when bit 8 of the V5 byte is set high  
for five or ten consecutive multiframes while RFI is recognized when bit 4 of V5 is  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
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