PMC-Sierra, Inc.
PM5356
S/UNI-622-MAX
DATASHEET
S/UNI-622-MAX
PMC-1980589
ISSUE 5
SATURN USER NETWORK INTERFACE (622-MAX)
This interface also indicates FIFO overruns via a maskable interrupt and register bit, but write
accesses while TCA is low are not processed. The TXCP automatically transmits idle cells until a
full cell is available to be transmitted.
UTOPIA Level 3 Interface
The UTOPIA Level 3 compliant interface accepts a write clock (TFCLK), a write enable signal
(TENB), the start of a cell (TSOC) indication and the parity bit (TPRTY) when data is written to the
transmit FIFO (using the rising edges of the TFCLK). To reduce FIFO latency, the FIFO depth at
which TCA indicates “full” can be set to one, two, three or four cells by the FIFODP[1:0] bits of the
TXCP Configuration 2 register. If the programmed depth is less than four, more than one cell
may be written after TCA is asserted as the TXCP still allows four cells to be stored in its FIFO.
The interface also indicates FIFO overruns via a maskable interrupt and register bits. The TXCP
automatically transmits idle cells until a full cell is available to be transmitted.
10.13 JTAG Test Access Port
The JTAG Test Access Port block provides JTAG support for boundary scan. The standard JTAG
EXTEST, SAMPLE, BYPASS, IDCODE and STCTEST instructions are supported. The S/UNI-
622-MAX identification code is 0x253560CD hexadecimal.
10.14 Microprocessor Interface
The microprocessor interface block provides normal and test mode registers, and the logic
required to connect to the microprocessor interface. The normal mode registers are required for
normal operation, and test mode registers are used to enhance the testability of the S/UNI-622-
MAX. In the following section every register is documented and identified using the register
number (REG #). Addresses that are not shown are not used and must be treated as Reserved.
Table 3: Register Memory Map
Address
000
Register Description
S/UNI-622-MAX Master Reset and Identity
S/UNI-622-MAX Master Configuration #1
S/UNI-622-MAX Master Configuration #2
S/UNI-622-MAX Clock Monitors
001
002
003
004
S/UNI-622-MAX Master Interrupt Status #1
S/UNI-622-MAX Master Interrupt Status #2
S/UNI-622-MAX APS Control and Status
S/UNI-622-MAX Miscellaneous Configuration
S/UNI-622-MAX Auto Line RDI Control
S/UNI-622-MAX Auto Path RDI Control
005
006
007
008
009
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
59
PMC [ PMC-SIERRA, INC ]
