PMC-Sierra, Inc.
PM5356
S/UNI-622-MAX
DATASHEET
S/UNI-622-MAX
PMC-1980589
ISSUE 5
SATURN USER NETWORK INTERFACE (622-MAX)
Register 0x63: RXCP Interrupt Enable and Counter Status
Bit
Bit 7
Type
Function
Default
R
R
XFERI
OVR
X
X
X
0
0
0
0
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unused
XFERE
OOCDE
HCSE
R/W
R/W
R/W
R/W
R/W
FOVRE
LCDE
LCDE:
The LCDE bit enables the generation of an interrupt due to a change in the LCD state. When
LCDE is set high, the interrupt is enabled.
FOVRE:
The FOVRE bit enables the generation of an interrupt due to a FIFO overrun error condition.
When FOVRE is set high, the interrupt is enabled.
HCSE:
The HCSE bit enables the generation of an interrupt due to the detection of a corrected or an
uncorrected HCS error. When HCSE is set high, the interrupt is enabled.
OOCDE:
The OOCDE bit enables the generation of an interrupt due to a change in cell delineation
state. When OOCDE is set high, the interrupt is enabled.
XFERE:
The XFERE bit enables the generation of an interrupt when an accumulation interval is
completed and new values are stored in the RXCP Count registers. When XFERE is set
high, the interrupt is enabled.
OVR:
The OVR bit is the overrun status of the RXCP Performance Monitoring Count registers. A
logic one in this bit position indicates that a previous transfer (indicated by XFERI being logic
one) has not been acknowledged before the next accumulation interval has occurred and that
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159
PMC [ PMC-SIERRA, INC ]
