PMC-Sierra, Inc.
PM5356
S/UNI-622-MAX
DATASHEET
S/UNI-622-MAX
PMC-1980589
ISSUE 5
SATURN USER NETWORK INTERFACE (622-MAX)
Register 0x62: RXCP FIFO/UTOPIA Control and Configuration
Bit
Bit 7
Type
Function
Default
R/W
RXPTYP
Unused
0
X
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
RCAINV
RCALEVEL0
Unused
1
X
X
X
0
Unused
Unused
R/W
FIFORST
FIFORST:
The FIFORST bit is used to reset the four-cell receive FIFO. When FIFORST is set low, the
FIFO operates normally. When FIFORST is set high, the FIFO is immediately emptied and
ignores writes. The FIFO remains empty and continues to ignore writes until a logic zero is
written to FIFORST. Activating this bit during a cell transfer may result in a truncated cell on
the System Interface.
RCALEVEL0:
The RCA level 0 bit, RCALEVEL0, determines when the RCA transitions low for Level 2
operation. When RCALEVEL0 is set high, a high-to-low transition on output RCA indicates
that the receive FIFO is empty and RCA will de-assert on the rising RFCLK edge after word
27 (of the 27 word cell structure) is output. When RCALEVEL0 is set low, a high-to-low
transition on output RCA indicates that the receive FIFO is near empty and RCA will de-
assert on the rising RFCLK edge after word 13 (of the 27 word cell structure) is output.
RCALEVEL0 must be set high when the system interface is configured for Level 3 operation.
RCAINV:
The RCAINV bit inverts the polarity of the RCA output signal for Level 2 operation. When
RCAINV is a logic one, the polarity of RCA is inverted (RCA at logic zero means there is a
receive cell available to be read). When RCAINV is a logic zero, the polarity of RCA is not
inverted.
RCAINV must be set low when the system interface is configured for Level 3 operation.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
157
PMC [ PMC-SIERRA, INC ]
