Pm49FL002 / 004
PMC
LPC MODE OPERATION
LPC MODE MEMORY READ/WRITE OPERATION
In LPC mode, the Pm49FL002/004 use the 5-pin LPC
interface includes 4-bit LAD[3:0] and LFRAME# pins to
communicate with the host system. The addresses and
data are transmitted through the 4-bit LAD[3:0] bus syn-
chronized with the input clock on CLK pin during a LPC
memory cycle operation. The address or data on LAD[3:0]
bus is latched on the rising edge of the clock. The pulse
of LFRAME# signal inserted for one or more clocks
indicates the start of a LPC memory read or write cycle.
Once the LPC memory cycle is started, asserted by
LFRAME#, a START value “0000b” is expected by the
devices as a valid command cycle. Then a CYCTYPE +
DIR value (“010xb” for memory read cycle or “011xb” for
memory write cycle) is used to indicates the type of
memory cycle. Refer to Table 4 and 5 for LPC Memory
Read and Write Cycle Definition.
There are 8 clock fields in a LPC memory cycle that
gives a 32 bit memory address A31 - A0 through LAD[3:0]
with the most-significant nibble first. The memory space
of Pm49FL002/004 are mapped directly to top of 4 Gbyte
system memory space. See Table 11 for System Memory
Map.
The Pm49FL002 is mapped to the address location of
(FFFFFFFFh - FFFC0000h), the A31- A18 must be
loaded with “1” to select and activate the device during a
LPC memory read or write operation. Only A17 - A0 is
used to decode and access the 256 Kbyte memory. The
I/O7 - I/O0 data is loaded onto LAD[3:0] in 2 clock cycles
with least-significant nibble first and most-significant
nibble last.
The Pm49FL004 is mapped to the address location of
(FFFFFFFFh - FFF80000h), the A31- A19 must be
loaded with “1” to select and activate the device during a
LPC memory operation. Only A18 - A0 is used to de-
code and access the 512 Kbyte memory.
Issue Date: December, 2003 Rev: 1.4
Programmable Microelectronics Corp.
16
PMC [ PMC-SIERRA, INC ]
