STANDARD PRODUCT
PM4351 COMET
DATA SHEET
PMC-1970624
ISSUE 10
COMBINED E1/T1 TRANSCEIVER
Register 011H: CDRC Interrupt Control
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
R/W
R/W
LCVE
LOSE
0
0
LCSDE
ZNDE
0
0
Unused
Unused
Unused
Unused
X
X
X
X
When the RUNI bit of the Receive Line Interface Configuration register is a logic
1, this register is held reset.
The bit positions LCVE, LOSE, LCSDE and ZNDE (bits 7 to 4) of this register are
interrupt enables to select which of the status events (Line Code Violation , Loss
Of Signal, HDB3 signature, B8ZS signature or N Zeros), either singly or in
combination, are enabled to generate an interrupt on the microprocessor INTB
pin when they are detected. A logic 1 bit in the corresponding bit position
enables the detection of these signals to generate an interrupt; a logic 0 bit in the
corresponding bit position disables that signal from generating an interrupt.
When the COMET is reset, LCVE, LOSE, LCSDE and ZNDE are set to logic 0,
disabling these events from generating an interrupt.
PROPRIETARY AND CONFIDENTIAL
110
PMC [ PMC-SIERRA, INC ]
