STANDARD PRODUCT
PM4351 COMET
DATA SHEET
PMC-1970624
ISSUE 10
COMBINED E1/T1 TRANSCEIVER
Register 010H: CDRC Configuration
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
AMI
0
0
0
0
0
0
0
0
LOS[1]
LOS[0]
Reserved
Reserved
ALGSEL
O162
Reserved
When the RUNI bit of the Receive Line Interface Configuration register is a logic
1, this register is held reset.
Reserved:
These bits must be a logic 0 for correct operation.
O162:
If the AMI bit is logic 0 in E1 mode, the Recommendation O.162 compatibility
select bit (O162) allows selection between two line code violation definitions:
If O162 is a logic 0, a line code violation is indicated if the serial stream does
not match the verbatim HDB3 definition given in Recommendation G.703. A
bipolar violation that is not part of an HDB3 signature or a bipolar violation in
an HDB3 signature that is the same polarity as the last bipolar violation
results in a line code violation indication.
If O162 is a logic 1, a line code violation is indicated if a bipolar violation is of
the same polarity as the last bipolar violation, as per Recommendation
O.162.
The O162 bit has no effect in T1 mode.
ALGSEL:
The Algorithm Select (ALGSEL) bit specifies the algorithm used by the DPLL
for clock and data recovery. The choice of algorithm determines the high
frequency input jitter tolerance of the CDRC. When ALGSEL is set to logic 1,
the CDRC jitter tolerance is increased to approach 0.5 UIpp for jitter
PROPRIETARY AND CONFIDENTIAL
108
PMC [ PMC-SIERRA, INC ]
