STANDARD PRODUCT
PM4351 COMET
DATA SHEET
PMC-1970624
ISSUE 10
COMBINED E1/T1 TRANSCEIVER
Register 002H: Receive Options
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RJATBYP
UNF
1
0
0
0
0
0
0
0
RXELSTBYP
RSYNC_MEM
RSYNCSEL
WORDERR
CNTNFAS
CCOFA
This register allows software to configure the receive functions of each framer.
RJATBYP:
The RJATBYP bit disables jitter attenuation in the receive direction. When
receive jitter attenuation is not being used, setting RJATBYP to logic 1 will
reduce the latency through the receiver section by typically 40 bits. When
RJATBYP is set to logic 0, the RSYNC output and the BRCLK output (if
BRCLK is configured to be an output by setting the CMODE bit of the
Receive Backplane Configuration register to logic 0), are jitter attenuated.
When the RJAT is bypassed, RSYNC and BRCLK are not jitter attenuated.
UNF:
The UNF bit allows the framer to operate with unframed DS-1 or E1 data.
When UNF is set to logic 1, the framer is disabled (both the T1-FRMR and
E1-FRMR are held reset) and the recovered data passes through the receiver
section of the framer without frame or channel alignment. While UNF is set
to logic 1, the Alarm Integrator continues to operate and detects and
integrates AIS alarm. When UNF is set to logic 0, the framer operates
normally, searching for frame alignment on the incoming data.
When UNF is a logic 1, the BRFP pin (if configured as an output) is held low.
RXELSTBYP:
The RXELSTBYP bit allows the Receive Elastic Store (RX-ELST) to be
bypassed, eliminating the one frame delay incurred through the RX-ELST.
When set to logic 1, the received data and clock inputs to RX-ELST are
internally routed directly to the RX-ELST output.
PROPRIETARY AND CONFIDENTIAL
80
PMC [ PMC-SIERRA, INC ]
