STANDARD PRODUCT
PM4351 COMET
DATA SHEET
PMC-1970624
ISSUE 10
COMBINED E1/T1 TRANSCEIVER
Register 04AH: T1 FRMR Interrupt Status
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R
R
R
R
R
R
R
R
COFAI
FERI
BEEI
SFEI
MFPI
INFRI
MFP
0
0
0
0
0
0
0
0
INFR
When the E1/T1B bit of the Global Configuration register is a logic 1 or the UNF
bit of the Receive Options register is a logic 1, this register is held reset.
This register indicate whether a change of frame alignment, a framing bit error, a
bit error event, or a severely errored framing event generated an interrupt. This
register also indicates whether a mimic framing pattern was detected or whether
there was a change in the "inframe" state of the frame circuitry.
COFAI, FERI, BEEI, SFEI:
A logic 1 in the status bit positions COFAI, FERI, BEEI and SFEI indicate that
the occurrence of the corresponding event generated an interrupt; a logic 0 in
the status bit positions COFAI, FERI, BEEI, and SFEI indicate that the
corresponding event did not generate an interrupt.
MFPI:
A logic 1 in the MFPI status bit position indicates that the assertion or
deassertion of the mimic detection indication has generated an interrupt; a
logic 0 in the MFPI bit position indicates that no change in the state of the
mimic detection indication occurred.
INFRI:
A logic 1 in the INFRI status bit position indicates that a change in the
"inframe" state of the frame alignment circuitry generated an interrupt; a
logic 0 in the INFRI status bit position indicates that no state change
occurred.
PROPRIETARY AND CONFIDENTIAL
170
PMC [ PMC-SIERRA, INC ]
