STANDARD PRODUCT
PM4351 COMET
DATA SHEET
PMC-1970624
ISSUE 10
COMBINED E1/T1 TRANSCEIVER
Register 048H: T1 FRMR Configuration
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
M2O[1]
M2O[0]
ESFFA
ESF
0
0
0
0
0
0
0
X
FMS1
FMS0
JPN
Unused
When the E1/T1B bit of the Global Configuration register is a logic 1 or the UNF
bit of the Receive Options register is a logic 1, this register is held reset.
This register selects the framing format and the frame loss criteria used by the
T1-FRMR.
M2O[1:0]:
The M2O[1:0] bits select the ratio of errored to total framing bits before
declaring out of frame in SF, SLC®96, and ESF framing formats. A logic 00
selects 2 of 4 framing bits in error; a logic 01 selects 2 of 5 bits in error; a
logic 10 selects 2 of 6 bits in error. In T1DM framing format, the ratio of
errored to total framing bits before declaring out of frame is always 4 out of
12. A logic 11 in the M2O[1:0] bits is reserved and should not be used.
ESFFA:
The ESFFA bit selects one of two framing algorithms for ESF frame search in
the presence of mimic framing patterns in the incoming data. A logic 0
selects the ESF algorithm where the FRMR does not declare inframe while
more than one framing bit candidate is following the framing pattern in the
incoming data. A logic 1 selects the ESF algorithm where a CRC-6
calculation is performed on each framing bit candidate, and is compared
against the CRC bits associated with the framing bit candidate to determine
the most likely framing bit position.
ESF:
The ESF bit selects either extended superframe format or enables the Frame
Mode Select bits to select either standard superframe, T1DM, or SLC®96
PROPRIETARY AND CONFIDENTIAL
166
PMC [ PMC-SIERRA, INC ]
