STANDARD PRODUCT
PM4351 COMET
DATA SHEET
PMC-1970624
ISSUE 10
COMBINED E1/T1 TRANSCEIVER
Register 04DH: IBCD Interrupt Enable/Status
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R
R
LBACP
LBDCP
LBAE
LBDE
LBAI
0
0
0
0
0
0
0
0
R/W
R/W
R
R
LBDI
R
LBA
R
LBD
When the E1/T1B bit of the Global Configuration register is a logic 1, this register
is held reset.
LBACP, LBDCP:
The LBACP and LBDCP bits indicate when the corresponding loopback code
is present during a 39.8 ms interval.
LBAE:
The LBAE bit enables the assertion or deassertion of the inband Loopback
Activate (LBA) detect indication to generate an interrupt on the
microprocessor INTB pin. When LBAE is set to logic 1, any change in the
state of the LBA detect indication generates an interrupt. When LBAE is set
to logic 0, no interrupt is generated by changes in the LBA detect state.
LBDE:
The LBDE bit enables the assertion or deassertion of the inband Loopback
Deactivate (LBD) detect indication to generate an interrupt on the
microprocessor INTB pin. When LBDE is set to logic 1, any change in the
state of the LBD detect indication generates an interrupt. When LBDE is set
to logic 0, no interrupt is generated by changes in the LBD detect state.
LBAI, LBDI:
The LBAI and LBDI bits indicate which of the two expected loopback codes
generated the interrupt when their state changed. A logic 1 in these bit
positions indicate that a state change in that code has generated an interrupt;
a logic 0 in these bit positions indicate that no state change has occurred.
PROPRIETARY AND CONFIDENTIAL
173
PMC [ PMC-SIERRA, INC ]
