STANDARD PRODUCT
PM4351 COMET
DATA SHEET
PMC-1970624
ISSUE 10
COMBINED E1/T1 TRANSCEIVER
Register 030H: BRIF Configuration
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
NXDS0[1]
NXDS0[0]
CMODE
DE
0
0
1
1
1
0
0
0
FE
CMS
RATE[1]
RATE[0]
NXDS0[1:0]:
The NXDS0[1:0] bits determine the mode of operation when BRCLK clock
master mode is selected, as shown in the following table. Note that these
bits are ignored when clock slave mode is selected.
Table 21
- Receive Backplane NXDS0 Mode Selection
NXDS0[1] NXDS0[0] Operation
0
0
1
1
0
1
0
1
Full Frame
56 kbit/s NxDS0
64 kbit/s NxDS0
64 kbit/s NxDS0 with F-bit (only valid for E1 mode)
When in Full Frame mode, the entire frame (193 bits for T1 or 256 bits for E1) is
presented and the BRCLK pulse train contains no gaps.
When in any of the NxDS0 modes, only those time slots with their DTRKC bit
cleared (logic 0) are clocked out the backplane. BRCLK does not pulse during
those time slots with their DTRKC bit set (logic 1). The DTRKC bits are located
in the RPSC Indirect Registers. When in T1 mode, the clock is always gapped
during the framing bit position.
When the 56 kbit/s NxDS0 mode is selected, only the first 7 bits of the selected
time slots are presented to the backplane and the 8th bit is gapped out. When
PROPRIETARY AND CONFIDENTIAL
137
PMC [ PMC-SIERRA, INC ]
