STANDARD PRODUCT
PM4351 COMET
DATA SHEET
PMC-1970624
ISSUE 10
COMBINED E1/T1 TRANSCEIVER
Register 02AH: RXCE Receive Data Link 2 Control
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DL2_EVEN
DL2_ODD
Unused
0
0
X
0
0
0
0
0
DL2_TS[4]
DL2_TS[3]
DL2_TS[2]
DL2_TS[1]
DL2_TS[0]
This register, along with the RXCE Data Link 2 Bit Select register, controls the
extraction of the data link terminated by RDLC #2. Refer to the "Using the
Internal HDLC Receivers" description in the Operation section for details on
terminating HDLC frames.
DL2_EVEN:
The data link 2 even select (DL2_EVEN) bit controls whether or not the
second data link is extracted from the even frames of the receive data
stream. If DL2_EVEN is a logic 0, the data link is not extracted from the even
frames. If DL2_EVEN is a logic 1, the data link is extracted from the even
frames. In E1 mode, the frames in an E1 CRC-4 multiframe are considered to
be numbered from 0 to 15; in T1 mode, the frames in a superframe are
considered to be numbered from 1 to 12 (or 1 to 24 in an extended
superframe).
DL2_ODD:
The data link 2 odd select (DL2_ODD) bit controls whether or not the second
data link is extracted from the odd frames of the receive data stream. If
DL2_ODD is a logic 0, the data link is not extracted from the odd frames. If
DL2_ODD is a logic 1, the data link is extracted from the odd frames.
DL2_TS[4:0]:
The data link 2 time slot (DL2_TS[4:0]) bits gives a binary representation of
the time slot/channel from which the data link is to be extracted. Note that T1
channels 1 to 24 are mapped to values 0 to 23. The DL2_TS[4:0] bits have
no effect when DL2_EVEN and DL2_ODD are both a logic 0.
PROPRIETARY AND CONFIDENTIAL
133
PMC [ PMC-SIERRA, INC ]
