STANDARD PRODUCT
PM4351 COMET
DATA SHEET
PMC-1970624
ISSUE 10
COMBINED E1/T1 TRANSCEIVER
the 64 kbit/s NxDS0 mode is selected, all 8 bits of the selected time slots are
presented to the backplane.
The 64 kbit/s NxDS0 with F-bit mode is intended to support ITU recommendation
G.802 where 1.544 Mbit/s data is carried within a 2.048 Mbit/s data stream. This
mode is only valid when the E1/T1B register bit is a logic 1 (E1 mode is
selected). The operation is the same as the 64 NxDS0 mode, except that the
framing bit is presented during the first bit of time slot 26. To properly extract a
G.802 formatted T1, the DTRKC bits must be set to logic 0 for time slots 1
through 15 and 17 through 26, and the DTRKC bits must be set to logic 1 for
time slots 27 through 31.
CMODE:
The clock mode (CMODE) bit determines whether the BRCLK pin is an input
or output. When CMODE is a logic 0, clock master mode is selected and the
BRCLK output is derived from the integral clock synthesizer. Depending on
the mode of operation, BRCLK may have a burst frequency of up to
2.048 MHz and may be gapped to support sub-rate applications. In T1 mode,
CMODE can only be logic 0 if the backplane rate is 1.544 Mbit/s
(RATE[1:0]=00) and CMS=0. In E1 mode, CMODE can only be logic 0 if the
backplane rate is 2.048 Mbit/s (RATE[1:0]=01) and CMS=0.
When CMODE is a logic 1, clock slave mode is selected and BRCLK is an
input.
DE:
The data edge (DE) bit determines the edge of BRCLK on which BRPCM and
BRSIG are generated. If DE is a logic 0, BRPCM and BRSIG are updated on
the falling edge of BRCLK. If DE is a logic 1, BRPCM and BRSIG are
updated on the rising edge of BRCLK.
FE:
The framing edge (FE) bit determines the edge of BRCLK on which the frame
pulse (BRFP) pulse is sampled or updated. If FE is a logic 0, BRFP is
sampled or updated on the falling edge of BRCLK. If FE is a logic 1, BRFP is
sampled on the rising edge of BRCLK. In the case where FE is not equal to
DE, BRFP is sampled or updated one clock edge before BRPCM and BRSIG.
CMS:
The clock mode select (CMS) bit determines the BRCLK frequency multiple.
If CMS is a logic 0, BRCLK is at the backplane rate. If CMS is a logic 1,
BRCLK is at twice the backplane rate.
PROPRIETARY AND CONFIDENTIAL
138
PMC [ PMC-SIERRA, INC ]
