STANDARD PRODUCT
PM4351 COMET
DATA SHEET
PMC-1970624
ISSUE 10
COMBINED E1/T1 TRANSCEIVER
Register 028H: RXCE Receive Data Link 1 Control
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DL1_EVEN
DL1_ODD
T1_DL_EN
DL1_TS[4]
DL1_TS[3]
DL1_TS[2]
DL1_TS[1]
DL1_TS[0]
0
0
1
0
0
0
0
0
This register, along with the RXCE Data Link 1 Bit Select register, controls the
extraction of the data link terminated by RDLC #1. Refer to the "Using the
Internal HDLC Receivers" description in the Operation section for details on
terminating HDLC frames.
DL1_EVEN:
The data link 1 even select (DL1_EVEN) bit controls whether or not the first
data link is extracted from the even frames of the receive data stream. If
DL1_EVEN is a logic 0, the data link is not extracted from the even frames. If
DL1_EVEN is a logic 1, the data link is extracted from the even frames. In E1
mode, the frames in an E1 CRC-4 multiframe are considered to be numbered
from 0 to 15; in T1 mode, the frames in a superframe are considered to be
numbered from 1 to 12 (or 1 to 24 in an extended superframe).
DL1_ODD:
The data link 1 odd select (DL1_ODD) bit controls whether or not the first
data link is extracted from the odd frames of the receive data stream. If
DL1_ODD is a logic 0, the data link is not extracted from the odd frames. If
DL1_ODD is a logic 1, the data link is extracted from the odd frames.
T1_DL_EN:
The T1 data link enable bit allows the termination of the ESF or T1DM data
links when in T1 mode. If T1_DL_EN is a logic 1, the ESF, FMS1 and FMS0
bits of the T1 FRMR Configuration register determine the bit locations from
which the data link is extracted. When the T1_DL_EN bit is a logic 1, the
DL1_EVEN and DL1_ODD bits must both be set to logic 0. This bit must be
set to logic 0 when in E1 mode.
PROPRIETARY AND CONFIDENTIAL
130
PMC [ PMC-SIERRA, INC ]
