STANDARD PRODUCT
PM4351 COMET
DATA SHEET
PMC-1970624
ISSUE 10
COMBINED E1/T1 TRANSCEIVER
FIFORST is logic 0, writing to the Divider Control Registers N1 and N2 will
cause only the PLL to reset.
LIMIT:
Setting the LIMIT bit to logic 1 will limit the PLL jitter attenuation by enabling
the FIFO to increase or decrease the frequency of the smooth output clock
whenever the FIFO is within one UI of overflowing or underflowing. This
limiting of jitter ensures that no data is lost during high phase shift conditions.
When LIMIT is set to logic 0, underflows and overflows may occur.
The recommended value of LIMIT is logic 0.
PROPRIETARY AND CONFIDENTIAL
124
PMC [ PMC-SIERRA, INC ]
