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PM4351-NI 参数 Datasheet PDF下载

PM4351-NI图片预览
型号: PM4351-NI
PDF下载: 下载PDF文件 查看货源
内容描述: 联合E1 / T1收发器 [COMBINED E1/T1 TRANSCEIVER]
分类和应用: 数字传输控制器电信集成电路电信电路PC
文件页数/大小: 485 页 / 3011 K
品牌: PMC [ PMC-SIERRA, INC ]
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STANDARD PRODUCT  
PM4351 COMET  
DATA SHEET  
PMC-1970624  
ISSUE 10  
COMBINED E1/T1 TRANSCEIVER  
of basic frame, when CRC-4-to-non-CRC-4 interworking is declared, and  
when the offline framer is out of frame.  
This bit only has effect in E1 mode.  
SIGAEN:  
The SIGAEN bit enables the operation of the signaling aligner (SIGA) to  
ensure superframe alignment of signaling bits between the backplane and the  
transmit DS-1 stream. When set to logic 1, the SIGA is inserted into the  
signaling bit data path before the T1-XBAS. When the signaling aligner is  
used, the backplane frame alignment indication must also be changed to  
indicate superframe alignment for the transmit backplane. When SIGAEN is  
set to logic 0, the SIGA is removed from the circuit. It is recommended that  
SIGAEN be set to logic 1 in T1 mode.  
This bit has no effect in E1 mode.  
OOCMFE0:  
When in E1 mode, the OOCMFE0 bit selects between two modes of  
operation concerning the transmission of E-bits when the COMET is out of  
CRC-4 multiframe. When OOCMFE0 is logic 0, the COMET transmits ones  
for the E-bits while out of CRC-4 multiframe. When OOCMFE0 is logic 1, the  
COMET transmits zeroes for the E-bits while out of CRC-4 multiframe. The  
option to transmit zeroes as E-bits while out of CRC-4 multiframe is provided  
to allow compliance with the CRC-4 to non-CRC-4 interworking procedure in  
Annex B of G.706.  
This bit only has effect in E1 mode.  
FDIS:  
The FDIS bit allows the framing generation through the transmitter to be  
disabled and the transmit data to pass through the transmitter unchanged.  
When FDIS is set to logic 1, the transmitter is disabled from generating  
framing. When FDIS is set to logic 0, the transmitter is enabled to generate  
and insert the framing into the transmit data.  
FBITBYP:  
The FBITBYP bit allows the frame synchronization bit in the input data  
stream, BTPCM, to bypass the generation through the XBAS and be re-  
inserted into the appropriate position in the digital output stream. When  
FBITBYP is set to logic 1, the input frame synchronization bit is re-inserted  
into the output data stream. When FBITBYP is set to logic 0, the XBAS is  
allowed to generate the output frame synchronization bits.  
PROPRIETARY AND CONFIDENTIAL  
88  
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