STANDARD PRODUCT
PM4351 COMET
DATA SHEET
PMC-1970624
ISSUE 10
COMBINED E1/T1 TRANSCEIVER
OCLKSEL1 OCLKSEL0 Source of FIFO Output Clock
1
X
The TJAT FIFO output clock is driven with the
FIFO input clock. In this mode the jitter
attenuation is disabled and the input clock must
be jitter-free. In this mode, PLLREF[1:0] must be
programmed to ‘b00.
PLLREF1, PLLREF0:
The PLLREF[1:0] bits select the source of the Transmit Jitter Attenuator
phase locked loop reference signal as follows:
Table 18
- TJAT PLL Source
PLLREF1 PLLREF0 Source of PLL Reference
0
0
TJAT FIFO input clock (either the conditioned BTCLK
or the receive recovered clock, as selected by
LINELB, assuming the TX-ELST is bypassed)
0
1
conditioned BTCLK input (assuming the TX-ELST is
bypassed)
1
1
0
1
Receive recovered clock
TCLKI input
If the BTCLK is configured as an output (CMODE bit of the Transmit
Backplane Configuration register is a logic 0), only the recovered clock or the
TCLKI input should be selected, or else the timing becomes self-referential
and unpredictable.
The following table illustrates the required bit settings for these various clock
sources to affect the transmitted data:
Table 19
- Transmit Timing Options Summary
Input Transmit Data
Bit Settings
OCLKSEL1=0
OCLKSEL0=0
PLLREF1=0
PLLREF0=X
LINELB=0
Effect on Output Transmit Data
Synchronous to BTCLK input.
Jitter attenuated. TCLKO is a smooth 1.544 MHz or
2.048 MHz.
Transmit Backplane Configuration
register CMODE =1.
TCLKO referenced to BTCLK input. TX-ELST
bypassed.
TXELSTBYP=1
PROPRIETARY AND CONFIDENTIAL
91
PMC [ PMC-SIERRA, INC ]
