PM4341AT1XC
DATA SHEET
PMC-900602
ISSUE 7
T1 FRAMER/TRANSCEIVER
Pin
Pin No.
Name
Type
PQFP PLCC Function
TDLCLK/
Output 67
66
Transmit Data Link Clock (TDLCLK). The
TDLCLK signal is available on this output
when the internal HDLC transmitter
(XFDL) is disabled from use. The rising
edge of TDLCLK is used to sample the
data stream contained on the TDLSIG
input. When the T1XC is configured to
transmit SF formatted data, the TDLCLK
output is held low.
TDLUDR
TCLKO
Transmit Data Link Underrun (TDLUDR).
The TDLUDR signal is available on this
output when XFDL is enabled. TDLUDR
goes high when the processor has failed
to service the TDLINT interrupt before
the transmit buffer is emptied.
Output 72
3
Transmit Clock Output (TCLKO). The
TDP, TDN, and TDD outputs may be
enabled to be updated on the rising or
falling edge of TCLKO. The TAP and TAN
outputs are also driven with timing
derived from TCLKO. TCLKO is a 1.544
MHz clock that is adequately jitter and
wander free in absolute terms to permit
an acceptable DSX-1 or DS-1 signal to
be generated. Depending on the
configuration of the T1XC, TCLKO may
be derived from TCLKI, RCLKO, or
BTCLK, with or without jitter attenuation.
TDP/
Output 71
2
Transmit Digital Positive Line Pulse
(TDP). This signal is available on the
output when the T1XC is configured to
transmit dual-rail data. The TDP signal
can be formatted for either RZ or NRZ
waveforms, and can be enabled to be
updated on the rising or falling edge of
TCLKO.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
27
PMC [ PMC-SIERRA, INC ]
