PM4341AT1XC
DATA SHEET
PMC-900602
ISSUE 7
T1 FRAMER/TRANSCEIVER
Pin
Pin No.
Name
Type
PQFP PLCC Function
BTCLK
Input
74
5
Backplane Transmit Clock (BTCLK). This
clock should be either 1.544MHz or
2.048MHz with optional gapping for
adaptation from non-uniform backplane
data streams. The T1XC may be
configured to ignore the BTCLK input
and use the RCLKO signal in its place.
TDLSIG/
I/O
66
65
Transmit Data Link Signal (TDLSIG). The
TDLSIG signal is input on this pin when
the internal HDLC transmitter (XFDL) is
disabled from use. TDLSIG is the source
for the data stream to be inserted into the
ESF data link. When the T1XC is
configured to transmit SLC®96
formatted data, the TDLSIG input is the
source for the Fs framing bits; when the
T1XC is configured to transmit T1DM
with R-bit replacement, TDLSIG is the
source of the R-bit in the T1DM sync
word. TDLSIG is sampled on the rising
edge of TDLCLK.
TDLINT
Transmit Data Link Interrupt (TDLINT).
The TDLINT signal is output on this pin
when XFDL is enabled. TDLINT goes
high when the last data byte written to
the XFDL has been set up for
transmission and processor intervention
is required to either write control
information to end the message, or to
provide more data.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
26
PMC [ PMC-SIERRA, INC ]
