PM4341AT1XC
DATA SHEET
PMC-900602
ISSUE 7
T1 FRAMER/TRANSCEIVER
Register 53H: RPSC Channel Indirect Data Buffer
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
This register contains either the data to be written into the internal RPSC
registers when a write request is initiated or the data read from the internal
RPSC registers when a read request has completed. During normal operation, if
data is to be written to the internal registers, the byte to be written must be
written into this Data register before the target register's address and R/WB=0 is
written into the Address/Control register, initiating the access. If data is to be read
from the internal registers, only the target register's address and R/WB=1 is
written into the Address/Control register, initiating the request. After 640 ns, this
register will contain the requested data byte.
The internal RPSC registers control the per-channel functions on the Receive
PCM data, provide the per-channel Data Trunk Conditioning Code, and provide
the per-channel Signalling Trunk Conditioning Code. The functions are allocated
within the registers as follows:
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
177
PMC [ PMC-SIERRA, INC ]
