PM4341AT1XC
DATA SHEET
PMC-900602
ISSUE 7
T1 FRAMER/TRANSCEIVER
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FEATURES
Integrates a full-featured T1 framer and line interface in a single device with
analog circuitry for receiving and transmitting DSX-1 compatible signals and
digital circuitry for terminating the duplex DS-1 signal.
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Provides an 8-bit microprocessor bus interface for configuration, control, and
status monitoring.
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Low power CMOS technology
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Available in either a 68 pin PLCC package, or a high density (14 by 14mm) 80
pin PQFP package.
The receiver section:
Provides analog circuitry for receiving a DSX-1 signal up to 655 feet from the
cross-connect. Direct digital inputs are also provided to allow for by-passing
the analog front-end.
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Recovers clock and data using a digital phase locked loop for high jitter
tolerance. A direct clock input is provided to allow clock recovery to be by-
passed.
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Accepts dual rail or single rail digital PCM inputs.
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Supports B8ZS or AMI line code.
Accepts gapped data streams to support higher rate demultiplexing.
Frames to SF, ESF, T1DM (DDS), and SLC®96 format DS1 signals.
Provides loss of signal detection, and red, yellow, and AIS alarm detection.
Red, yellow, and AIS alarms are integrated as per industry specifications.
Detects violations of the ANSI T1.403 12.5% pulse density rule over a moving
192 bit window.
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Provides programmable in-band loopback code detection.
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Supports line and path performance monitoring according to AT&T and ANSI
specifications. Accumulators are provided for counting:
ESF CRC-6 errors to 333 per second;
Framing bit errors to 31 per second;
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Line code violations to 4095 per second; and
Loss of frame or change of frame alignment events to 7 per
second.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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PMC [ PMC-SIERRA, INC ]
