PM4341AT1XC
DATA SHEET
PMC-900602
ISSUE 7
T1 FRAMER/TRANSCEIVER
TABLE 23 - TEST MODE 0 PRIMARY INPUT READING MAP.....................194
TABLE 24 - TEST MODE 0 PRIMARY OUTPUT WRITING MAP..................195
TABLE 25 - DEFAULT SETTINGS .................................................................209
TABLE 26 - ESF FRAME FORMAT ...............................................................210
TABLE 27 - SLC®96 FRAME FORMAT.........................................................211
TABLE 28 - SF FRAME FORMAT..................................................................212
TABLE 29 - T1DM FRAME FORMAT.............................................................213
TABLE 30 - PMON POLLING SEQUENCE...................................................213
TABLE 31 - ESF FDL PROCESSING............................................................214
TABLE 32 - TYPICAL OUTPUT VOLTAGES FOR XPLS CODES..................230
TABLE 33 - PREPROGRAMMED XPLS CODE SEQUENCES.....................231
TABLE 34 - PMON COUNTER SATURATION CHARACTERISTICS ............236
TABLE 35 - SETTING UP T1XC TO PROCESS THE D-CHANNEL ..............242
TABLE 36 - D.C. CHARACTERISTICS ..........................................................247
TABLE 37 - MICROPROCESSOR READ ACCESS ......................................249
TABLE 38 - MICROPROCESSOR WRITE ACCESS.....................................251
TABLE 39 - BACKPLANE TRANSMIT INPUT TIMING (FIGURE 57)............254
TABLE 40 - XCLK=37.056MHZ INPUT (FIGURE 58)....................................255
TABLE 41 - TCLKI INPUT (FIGURE 59)........................................................256
TABLE 42 - DIGITAL RECEIVE INTERFACE INPUT TIMING (FIGURE 60) .256
TABLE 43 - TRANSMIT DATA LINK INPUT TIMING (FIGURE 61)................258
TABLE 44 - BACKPLANE RECEIVE INPUT TIMING (FIGURE 62) ..............258
TABLE 45 - RECEIVE DATA LINK OUTPUT TIMING (FIGURE 63) ..............259
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
xiv
PMC [ PMC-SIERRA, INC ]
