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PM4341A-QI 参数 Datasheet PDF下载

PM4341A-QI图片预览
型号: PM4341A-QI
PDF下载: 下载PDF文件 查看货源
内容描述: T1成帧器/收发器 [T1 FRAMER/TRANSCEIVER]
分类和应用: 数字传输控制器电信集成电路电信电路
文件页数/大小: 288 页 / 981 K
品牌: PMC [ PMC-SIERRA, INC ]
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PM4341AT1XC  
DATA SHEET  
PMC-900602  
ISSUE 7  
T1 FRAMER/TRANSCEIVER  
FIGURE 43- CODE REGISTER SEQUENCE DURING PULSE GENERATION...  
.....................................................................................................232  
FIGURE 44- CODE REGISTER SEQUENCE FOR 0-110 FEET BUILD-OUT233  
FIGURE 45- LCV COUNT VS. BER................................................................236  
FIGURE 46- FER COUNT VS. BER FOR SF AND T1DM FRAMING FORMATS .  
.....................................................................................................237  
FIGURE 47- FER COUNT VS. BER FOR SLC®96 FRAMING FORMAT........237  
FIGURE 48- FER COUNT VS. BER FOR ESF FRAMING FORMAT ..............238  
FIGURE 49- BEE COUNT VS. BER FOR ESF FRAMING FORMAT ..............238  
FIGURE 50- BEE COUNT VS. BER FOR SF FRAMING FORMAT.................239  
FIGURE 51- BEE COUNT VS. BER FOR SLC®96 FRAMING FORMAT........239  
FIGURE 52- BEE COUNT VS. BER FOR T1DM FRAMING FORMAT............240  
FIGURE 53- EXAMPLE 4.TERMINATING ISDN PRIMARY RATE D-CHANNEL  
WITH QFDL.....................................................................................................241  
FIGURE 54- EXAMPLE 5.TERMINATING ISDN PRIMARY RATE D-CHANNEL  
WITH VL1935..................................................................................................243  
FIGURE 55- MICROPROCESSOR READ ACCESS TIMING.........................250  
FIGURE 56- MICROPROCESSOR WRITE ACCESS TIMING .......................252  
FIGURE 57- BACKPLANE TRANSMIT INPUT TIMING DIAGRAM ................254  
FIGURE 58- XCLK=37.056MHZ INPUT TIMING ............................................255  
FIGURE 59- TCLKI INPUT TIMING ................................................................256  
FIGURE 60- DIGITAL RECEIVE INTERFACE INPUT TIMING DIAGRAM......257  
FIGURE 61- TRANSMIT DATA LINK INPUT TIMING DIAGRAM ....................258  
FIGURE 62- BACKPLANE RECEIVE INPUT TIMING DIAGRAM...................258  
FIGURE 63- RECEIVE DATA LINK OUTPUT TIMING DIAGRAM...................259  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
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