PM4341AT1XC
DATA SHEET
PMC-900602
ISSUE 7
T1 FRAMER/TRANSCEIVER
enabled; when SIGC1 is set to logic 0, the insertion of signalling bits is disabled.
For SF and SLC®96 formats, the C' and D' or C and D bits from Signalling
Control byte or BTSIG, respectively, are inserted into the A and B signalling bit
positions of every second superframe that is transmitted. It is assumed that C=A
and D=B.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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