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PM4328-PI 参数 Datasheet PDF下载

PM4328-PI图片预览
型号: PM4328-PI
PDF下载: 下载PDF文件 查看货源
内容描述: 高密度T1 / E1成帧器,集成M13多路复用器 [HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED M13 MULTIPLEXER]
分类和应用: 复用器数字传输控制器电信集成电路电信电路异步传输模式ATM
文件页数/大小: 250 页 / 1399 K
品牌: PMC [ PMC-SIERRA, INC ]
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STANDARD PRODUCT  
PM4328 TECT3  
DATASHEET  
PMC-2011596  
ISSUE 1  
HIGH DENSITY T1/E1 FRAMER  
AND M13 MULTIPLEXER  
9.18 Receive and Transmit Digital Jitter Attenuator (RJAT, TJAT)  
The Digital Jitter Attenuation function is provided by the DJAT blocks. Each  
framer in the TECT3 contains two separate jitter attenuators, one between the  
receive demultiplexed or demapped T1 or E1 link and the ingress interface  
(RJAT) and the other between the egress interface and the transmit T1 or E1 link  
to be multiplexed into DS3 (TJAT). Each DJAT block receives jittered data and  
stores the stream in a FIFO timed to the associated receive jittered clock. The  
jitter attenuated data emerges from the FIFO timed to the jitter attenuated clock.  
In the RJAT, the jitter attenuated clock (ICLK[x]) is referenced to the  
demultiplexed tributary receive clock. In the TJAT, the jitter attenuated transmit  
tributary clock feeding the M13 multiplexer may be referenced to either CTCLK,  
CECLK, or the tributary receive clock.  
In T1 mode each jitter attenuator generates its output clock by adaptively dividing  
the 37.056 MHz XCLK signal according to the phase difference between the jitter  
attenuated clock and the input reference clock. Jitter fluctuations in the phase of  
the reference clock are attenuated by the phase-locked loop within each DJAT  
so that the frequency of the jitter attenuated clock is equal to the average  
frequency of the reference. To best fit the jitter attenuation transfer function  
recommended by TR 62411, phase fluctuations with a jitter frequency above 6.6  
Hz are attenuated by 6 dB per octave of jitter frequency. Wandering phase  
fluctuations with frequencies below 6.6 Hz are tracked by the jitter attenuated  
clock. The jitter attenuated clock (ICLK[x] for the RJAT and transmit clock for the  
TJAT) are used to read data out of the FIFO.  
In E1 mode each jitter attenuator generates the jitter-free 2.048 MHz output  
clock by adaptively dividing the 49.152 MHz XCLK signal according to the phase  
difference between the jitter attenuated clock and input reference clock.  
Fluctuations in the phase of the input data clock are attenuated by the phase-  
locked loop within DJAT so that the frequency of the jitter attenuated clock is  
equal to the average frequency of the input data clock. Phase fluctuations with a  
jitter frequency above 8.8 Hz are attenuated by 6 dB per octave of jitter  
frequency. Wandering phase fluctuations with frequencies below 8.8 Hz are  
tracked by the jitter attenuated clock. To provide a smooth flow of data out of  
DJAT, the jitter attenuated clock is used to read data out of the FIFO.  
The TJAT and RJAT have programmable divisors in order to generate the jitter  
attenuated clock from the various reference sources. The divisors are set using  
the TJAT and RJAT Jitter Attenuator Divider N1 and N2 registers. The following  
formula must be met in order to select the values of N1 and N2:  
Fin/(N1 + 1) = Fout/(N2 + 1)  
PROPRIETARY AND CONFIDENTIAL  
71