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PM4328-PI 参数 Datasheet PDF下载

PM4328-PI图片预览
型号: PM4328-PI
PDF下载: 下载PDF文件 查看货源
内容描述: 高密度T1 / E1成帧器,集成M13多路复用器 [HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED M13 MULTIPLEXER]
分类和应用: 复用器数字传输控制器电信集成电路电信电路异步传输模式ATM
文件页数/大小: 250 页 / 1399 K
品牌: PMC [ PMC-SIERRA, INC ]
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STANDARD PRODUCT  
PM4328 TECT3  
DATASHEET  
PMC-2011596  
ISSUE 1  
HIGH DENSITY T1/E1 FRAMER  
AND M13 MULTIPLEXER  
where Fin is the input reference clock frequency and Fout is the output jitter  
attenuated clock frequency. The values on N1 and N2 can range between 1 and  
256. Fin ranges from 8KHz to 2.048MHz in 8KHz increments.  
If the FIFO read pointer comes within one bit of the write pointer, DJAT will track  
the jitter of the input clock. This permits the phase jitter to pass through  
unattenuated, inhibiting the loss of data.  
Jitter Characteristics  
Each DJAT Block provides excellent jitter tolerance and jitter attenuation while  
generating minimal residual jitter. In T1 mode each DJAT can accommodate up  
to 28 UIpp of input jitter at jitter frequencies above 6 Hz. For jitter frequencies  
below 6 Hz, more correctly called wander, the tolerance increases 20 dB per  
decade. In E1 mode each DJAT can accommodate up to 35 UIpp of input jitter at  
jitter frequencies above 9 Hz. For jitter frequencies below 9 Hz, more correctly  
called wander, the tolerance increases 20 dB per decade. In most applications  
the each DJAT Block will limit jitter tolerance at lower jitter frequencies only. For  
high frequency jitter, above 10 kHz for example, other factors such as clock and  
data recovery circuitry may limit jitter tolerance and must be considered. For low  
frequency wander, below 10 Hz for example, other factors such as slip buffer  
hysteresis may limit wander tolerance and must be considered. The DJAT  
blocks meet the stringent low frequency jitter tolerance requirements of AT&T TR  
62411, ITU-T Recommendation G.823 and thus allow compliance with this  
standard and the other less stringent jitter tolerance standards cited in the  
references.  
The DJAT exhibits negligible jitter gain for jitter frequencies below 6.6 Hz, and  
attenuates jitter at frequencies above 6.6 Hz by 20 dB per decade in T1 mode. It  
exhibits negligible jitter gain for jitter frequencies below 8.8 Hz, and attenuates  
jitter at frequencies above 8.8 Hz by 20 dB per decade in E1 mode. In most  
applications the DJAT Blocks will determine jitter attenuation for higher jitter  
frequencies only. Wander, below 10 Hz for example, will essentially be passed  
unattenuated through DJAT. Jitter, above 10 Hz for example, will be attenuated  
as specified, however, outgoing jitter may be dominated by the generated  
residual jitter in cases where incoming jitter is insignificant. This generated  
residual jitter is directly related to the use of 24X (37.056 MHz or 49.152 MHz)  
digital phase locked loop for transmit clock generation. DJAT meets the jitter  
transfer requirements of AT&T TR 62411. The DJAT allows the implied T1 jitter  
attenuation requirements for a TE or NT1 given in ANSI Standard T1.408, and  
the implied jitter attenuation requirements for a type II customer interface given in  
ANSI T1.403 to be met. The DJAT meets the E1 jitter attenuation requirements  
of the ITU-T Recommendations G.737, G.738, G.739 and G.742.  
PROPRIETARY AND CONFIDENTIAL  
72  
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