STANDARD PRODUCT
PM4328 TECT3
DATASHEET
PMC-2011596
ISSUE 1
HIGH DENSITY T1/E1 FRAMER
AND M13 MULTIPLEXER
5. XCLK frequency must be 24x the line rate ±32 ppm when TJAT is free-
running or referenced to a derivative of XCLK. XCLK may be ± 100 ppm if an
accurate reference is provided to TJAT.
6. CTCLK can be a jittered clock signal subject to the minimum high and low
durations tHCTCLK, tLCTCLK. These durations correspond to nominal
XCLK input frequency.
7. When a set-up time is specified between an input and a clock, the set-up
time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4
Volt point of the clock.
8. When a hold time is specified between an input and a clock, the hold time is
the time in nanoseconds from the 1.4 Volt point of the clock to the 1.4 Volt
point of the input.
9. Setup, hold, and propagation delay specifications are shown relative to the
default active clock edge, but are equally valid when the opposite edge is
selected as the active edge.
10.Output propagation delay time is the time in nanoseconds from the 1.4 Volt
point of the reference signal to the 1.4 Volt point of the output.
11.Output propagation delays are measured with a 50 pF load on all outputs with
the exception of the high speed DS3 outputs (TCLK, TPOS/TDAT,
TNEG/TMFP). The TCLK, TPOS/TDAT, TNEG/TMFP output propagation
delays are measured with a 20 pF load.
PROPRIETARY AND CONFIDENTIAL
231
PMC [ PMC-SIERRA, INC ]
