STANDARD PRODUCT
PM4328 TECT3
DATASHEET
PMC-2011596
ISSUE 1
HIGH DENSITY T1/E1 FRAMER
AND M13 MULTIPLEXER
receive clock and data (shown as RxD[x] and RxCLK[x] in the diagnostic
loopback figure) The data flow through a single T1/E1 framer in this loopback
condition is illustrated in Figure 36.
Figure 36: T1/E1 Diagnostic Digital Loopback
CTCLK*
TRANSMITTER
T1-XBAS/E1-TRAN
TOPS
ED[1:28]
ESIF
Egress
BasicTransmitter:
Timing Options
Frame Generation,
Alarm Insertion,
Signaling
ECLK[1:28]/EFP[1:28]/
Interface
ESIG[1:28]
TJAT
TxCLK[1:28]
TxD[1:28]
Digital Jitter
Attenuator
CEFP*
CECLK*
Trunk Conditioning
Line Coding
Di agn ost i c Loopb ack
FRAM
CICLK*
CIFP*
Framer/
ELST
Slip Buffer
Elastic
Store
RAM
T1/E1-FRMR
Framer:
ID[1:28]
ICLK[1:28]/ISIG[1:28]
IFP[1:28]
RxCLK[1:28]
RxD[1:28]
RJAT
Frame
Digital Jitter
Attenuator
ISIF
Ingress
Interface
Alignment,
Alarm
Extraction
RECEIVER
Per-Channel Loopback
The T1/E1 payload may be looped-back on a per-channel basis through the use
of the TPSC. If all channels are looped-back, the result is very similar to Payload
Loopback on other PMC framers. In order for per-channel loopback to operate
correctly, the Ingress Interface must be in Clock Master mode. The LOOP bit
must be set to logic 1 in the TPSC Internal Registers for each channel desired to
be looped back, and the PCCE bit must be set to logic 1 in the TPSC
Configuration register. When all these configurations have been made, the
ingress DS0s or timeslots selected will overwrite their corresponding egress
channels; the remaining egress channels will pass through intact. Note that
because the egress and ingress streams will not be superframe aligned, that any
robbed-bit signaling in the ingress stream may not fall in the correct frame once
looped-back, and that egress robbed-bit signaling will overwrite the looped-back
channel data if signaling insertion is enabled. PRBS generation and detection is
PROPRIETARY AND CONFIDENTIAL
153
PMC [ PMC-SIERRA, INC ]
