PRELIMINARY
PM4318 OCTLIU
DATASHEET
PMC- 2001578
ISSUE 3
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 310H: INSBI Control
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
R/W
R/W
R/W
R/W
APAGE
DC_ENBL
DC_INT_EN
FIFO_OVRE
FIFO_UDRE
TS_EN
0
1
0
0
0
0
X
1
Unused
R/W
SBI_PAR_CTL
SBI_PAR_CTL:
The SBI_PAR_CTL bit is used to configure the Parity mode for generation of the SBI data
parity signal, DDP as follows:
•
•
When SBI_PAR_CTL is a ‘0’ parity will be even.
When SBI_PAR_CTL is a ‘1’ parity will be odd.
TS_EN:
The TS_EN bit is used to enable the SBI tributary to LIU octant data stream mapping
capability.
•
When TS_EN is a ‘0’, the mapping is fixed to a one to one mapping and is not
programmable. The 8 LIU data streams are mapped to tributaries 1 to 8 of SPE #1
within the SBI structure.
•
When TS_EN is a ‘1’, SBI tributary to LIU octant data stream mapping is enabled
and is specified by the contents of the INSBI Tributary Mapping registers.
FIFO_UDRE:
The FIFO_UDRE bit is used to enable/disable the generation of an interrupt when a FIFO
underrun is detected.
•
•
When FIFO_UDRE is a ‘0’ underrun interrupt generation is disabled.
When FIFO_UDRE is a ‘1’ underrun interrupt generation is enabled.
FIFO_OVRE:
The FIFO_OVRE bit is used to enable/disable the generation of an interrupt when a FIFO
overrun is detected.
•
When FIFO_OVRE is a ‘0’ overrun interrupt generation is disabled.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
81
PMC [ PMC-SIERRA, INC ]
