PRELIMINARY
PM4318 OCTLIU
DATASHEET
PMC- 2001578
ISSUE 3
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Table 6
– TJAT FIFO Output Clock Source
OCLKSEL
Source of FIFO Output Clock
0
The TJAT FIFO output clock is connected to the internal
jitter-attenuated 1.544 MHz or 2.048 MHz clock.
1
The TJAT FIFO output clock is connected to the FIFO input
clock. In this mode the jitter attenuation is disabled and the
input clock must be jitter-free. PLLREF[1:0] must be set to
“00” in this mode.
PLLREF:
The PLLREF bit selects the source of the Transmit Jitter Attenuator phase locked loop
reference signal as follows:
Table 7
– TJAT PLL Source
PLLREF[1:0]
Source of PLL Reference
00
TJAT FIFO input clock (either the transmit clock or the
receive recovered clock, as selected by LINELB)
01
Receive recovered clock
1X
CSU transmit clock (see Table 5)
Upon reset of the OCTLIU, the OCLKSEL and PLLREF bits are cleared to zero, selecting jitter
attenuation with transmit line clock referenced to the transmit clock, TCLK[n] (or the SBI tributary
clock). Figure 17 illustrates the various bit setting options, with the reset condition highlighted.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
74
PMC [ PMC-SIERRA, INC ]
