PM3350 ELAN 8 X10
ELAN 8X10
DATA SHEET
PMC-970109
ISSUE 3
8 PORT ETHERNET SWITCH
Memory read enable. This output signals the external memory banks that a
read is being performed and data should be output on the MDATA[31:0] lines
from the specified address. The MRD_ output may be tied to the OE* inputs of
standard memory devices.
MRD_
1
4
O
O
Memory write enables, used by the ELAN 8x10 to enable the data presented
on individual byte lanes of MDATA[31:0] to be individually written to memory.
MWE_[0] corresponds to MDATA[7:0], MWE_[1] corresponds to MDATA[15:8],
and so on. When using 2-CAS asynchronous DRAM devices, the MWE_[3:0]
outputs should be connected to the memory CAS* inputs; otherwise, the
MWE_[3:0] outputs should be connected to the appropriate byte write enables.
MWE_[3:0]
Global memory write enable. This signal is used to signal that a write access
is occurring, and should be connected to the WE* inputs of dual CAS
asynchronous DRAM devices.
MGWE_
MRDY_
1
1
O
I
Memory ready input. If an external memory timing generator is used, it can be
connected to the MRDY_ input to force the ELAN 8x10 to insert wait states into
memory accesses. If the MRDY_ line is de-asserted, the ELAN 8x10 will hold
the MADDR[15:0], MCS_[3:0], MRD_ and MWR_[3:0] lines at their present
values (as well as MDATA[31:0] for memory writes).
The MRDY* input is only sampled by the ELAN 8x10 when performing an
SRAM-type access; it is ignored for all other memory types. If an external
memory timing generator is not used, the MRDY_ line should be tied LOW.
Local interrupt input. The MINTR_ may be used to provide an interrupt input to
the ELAN 8x10 in special applications. If the MINTR_ input is not used, it
should be tied HIGH.
MINTR_
1
I
Clock Inputs and Outputs
Signal Name Size
Type Description
50 MHz master device clock input, This should be driven by a 50 MHz
symmetrical clock source with a duty cycle between 40% and 60%. It is re-timed
and driven out on the MEMCLK line, and is also used in the internal device
logic.
SYSCLK
1
I
50 MHz clock output derived from SYSCLK; supplies the re-timed 50 MHz clock
(input on the SYSCLK pin) to external devices.
MCLK
1
1
O
O
20 MHz clock output (for use by MAU devices). The 50 MHz input clock is
internally divided by 2.5 and output as an asymmetrical 20 MHz clock reference
on the CLK20 output; this clock may be used as an input to external MAU
devices.
CLK20
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND PMC-SIERRA, INC. CUSTOMERS ONLY
25
PMC [ PMC-SIERRA, INC ]
