PM3350 ELAN 8 X10
ELAN 8X10
DATA SHEET
PMC-970109
ISSUE 3
8 PORT ETHERNET SWITCH
PCI bus reset (system reset). Performs a hardware reset of the ELAN 8x10 and
associated peripherals when asserted. The RST_ input uses a Schmitt trigger to
accommodate slow rise and fall times, allowing a simple RC network to be used to
provide power-on reset capability.
RST_
1
I
MAU Interface Pins
Signal Name Size
Type Description
Transmit data outputs (to 8 MAUs). The TXD lines are used to carry outgoing
TXD[7:0]
8
O
data bytes to the Medium Access Units (MAUs). Each bit of the bus is
connected to the serial transmit data input of a separate MAU device. The
TXD[7:0] lines are synchronous to the TCLK[7:0] lines (TXD[0] to TCLK[0], and
so on). Data are driven on to the TXD[7:0] lines after the rising edge of the
corresponding TCLK[7:0] input, and may be sampled on the next rising edge of
the latter.
Transmit enables. The data carried on the TXD[7:0] lines is only valid when the
TEN[7:0] lines are active. This also indicates to the MAU devices that the ELAN
8x10 is acquiring the medium. Each of the TEN[7:0] lines should be connected
to a separate MAU device. The TEN[7:0] outputs are asserted or de-asserted on
the rising edge of the corresponding TCLK[7:0] input, and may be sampled on
the next rising edge of the latter.
TEN[7:0]
8
8
O
Transmit clocks; these inputs provide the synchronization references for the
TXD[7:0] and TEN[7:0] lines. TCLK[7:0] should be driven with a 10 MHz transmit
data clock reference by the external MAU devices (each MAU device should
drive a separate line of the TCLK[7:0] bus). Each of the TCLK[7:0] lines may be
driven completely asynchronously to all the others. The rising edges of the
TCLK[7:0] signals are used as timing references. The TCLK[7:0] inputs are
Schmitt-triggered for improved resistance to slow rise and fall times.
TCLK[7:0]
I
Receive data inputs (from 8 MAUs). The RXD lines transfer incoming serial
received data from the external MAU devices to the ELAN 8x10. Each bit of the
bus is connected to the serial receive data output of a separate MAU device.
The RXD[7:0] lines are sampled synchronously by the ELAN 8x10 at the rising
edges of the clocks supplied on the RCLK[7:0] inputs (RXD[0] to RCLK[0], and
so on).
RXD[7:0]
8
8
I
I
Receive clocks; should be driven by the external MAU devices with the receive
clock references recovered from the incoming serial receive data. The
RCLK[7:0] inputs need not be driven with a continuous clock reference;
however, they must be running whenever the CD[7:0] inputs are asserted, and
must continue running for at least five clock cycles after the CD[7:0] inputs
transition LOW in order to permit the internal MAC logic to function properly.
The RCLK[7:0] inputs are Schmitt-triggered for improved resistance to slow rise
and fall times.
RCLK[7:0]
Receive carrier detect signals. These carrier detect inputs should be driven with
the carrier detect (i.e., data being received from the medium) signals generated
by the eight external MAU devices, and are sampled synchronously to the rising
edges of the clocks input on the RCLK[7:0] lines and the TCLK[7:0] lines to
implement the CSMA/CD algorithm. The data presented on RXD[7:0] are only
sampled when the corresponding CD[7:0] lines are asserted HIGH. (If not all of
the eight ELAN 8x10 MAC ports are connected to external MAU devices, the CD
inputs for to the missing MAU devices should be tied LOW.)
CD[7:0]
8
I
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND PMC-SIERRA, INC. CUSTOMERS ONLY
23
PMC [ PMC-SIERRA, INC ]
